A 0,14 <$E mu roman m> CMOS transistor with 2 levels of interconnection is designed and simulated to investigate its functionality and characteristics. ATHENA and ATLAS simulators are used to simulate the fabrication process and to validate the electrical characteristics respectively. A scaling factor of 0,93 has been applied on a 0,13 <$E mu roman m> CMOS. The parameters being scaled are the effective channel length, the density of ion implantation for threshold voltage (<$E V sub roman th>) adjustment, and the gate oxide thickness. In order to minimize high field effects, the following additional techniques are implemented: shallow trench isolation (STI), sidewall spacer deposition, silicide formation, lightly doped drain (LDD) implantation, and retrograde well implantation. The results show that drain current (ID) increases as the levels of interconnection increases. The important parameters for NMOS and PMOS are measured. For NMOS, the gate length (<$E L sub g>) is 0,133 <$E mu roman m>, threshold voltage (<$E V sub roman th>) is 0,343138 V, and the gate oxide thickness (<$E T sub roman ox>) is 3,46138 nm. For PMOS, <$E L sub g> is 0,133 <$E mu roman m>, <$E V sub roman th> is -0,378108 V, and <$E T sub roman ox> is 3,46167 nm. These parameters are validated and the device is proven operational.

Індекс рубрикатора НБУВ: З844.1

Рубрики:

Мікрорадіоелектронна апаратура. Мікроелектроніка

Шифр НБУВ: Ж16425 Пошук видання у каталогах НБУВ 

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